1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which conducts a reliability test using a dynamic signal (Dynamic Voltage Stress Test).
2. Description of Related Art
A defective rate of a semiconductor device decreases with time in an initial period just after manufacturing (hereinafter, failure which is generated in this period is referred as initial failure”), and the defective rate becomes constant after a predetermined period has passed. When further time has passed, the defective rate increases. This is so-called bathtub curve. In semiconductor devices, to decrease the defective rate after shipment, an acceleration test and a function test after the acceleration test are conducted to prevent the shipping of the device having defect. A dynamic voltage stress/screening (DVS) test is one of the acceleration tests. In the DVS test, test data which toggles semiconductor elements is input continuously to accelerate time degradation of semiconductor elements.
When this DVS test is conducted to for example a memory which selects and accessed one element from a plurality of elements under a normal usage state, it is necessary to select one element and toggle the elements in series which is a time-consuming process. To solve this problem, Japanese Unexamined Patent Application Publications No. 5-282885, 11-297099, 11-120794, 2005-32375, and 10-283800 disclose methods for reducing the time of DVS test.
These patent applications each describe conducting the DVS test by a semiconductor device which includes a plurality of memory cells arranged in a matrix pattern. In these patent applications, when the DVS test is conducted, a plurality of rows or columns are selected and all test data are collectively written into memory cells arranged in the plurality of rows or columns. Here, the techniques of these patent applications reduce the time of the DVS test.